Embedded read only memories (ROMs) are widely utilized within processors. Such memories need to be both small in size and fast in operation. Embedded ROMs typically use a single transistor for each bit position, connected to a single bitline or not connected to the bitline for a logical one or zero at the respective bit position. However, the sensing device then needs to distinguish if the connection exists during a read. Typically the connection is sensed by detecting a significant pull-down on the bitline, which often involves waiting a significant period for transistor transition and/or settling times to elapse.
Other ROM designs employ two or more transistors for each bit position or storage cell within the memory to create a differential signal on two bitlines, allowing a very fast differential sense-amp quickly capture the value to be read. However, such a multi-transistor bit storage element is more costly in the size of the embedded memory.
There is, therefore, a need in the art for a memory permitting differential sensing with a single transistor bit element.